e/CoreConnect

Information
has gloss	eng: __NOTOC__ CoreConnect is a microprocessor bus architecture from IBM for system-on-a-chip (SoC) designs. Designed to ease the integration and reuse of processor, system, and peripheral cores within standard and custom SoC designs. It is a standard SoC design point, and serves as the foundation of IBM or non-IBM devices. Elements of this architecture include the processor local bus (PLB), the on-chip peripheral bus (OPB), a bus bridge, and a device control register (DCR) bus. High-performance peripherals connect to the high-bandwidth, low-latency PLB. Slower peripheral cores connect to the OPB, which reduces traffic on the PLB. There are bridging capabilities to the competing AMBA bus architecture allowing reuse of existing SoC-components.
lexicalization	eng: CoreConnect
instance of	e/Computer/bus