e/Interrupts in 65xx processors

Information
has gloss	eng: The detection of a RESET signal causes the processor to enter a system initialization period of six clock cycles, after which it sets the interrupt disable flag in the status register and loads the PC register with the values stored at in the relevant memory addresses (see table), before commencing execution. This requirement is eliminated when the 65802/65816 is operating in native mode, due to the separate vectors for the two interrupt types.
lexicalization	eng: Interrupts in 65xx processors
instance of	c/65xx microprocessors