| has gloss | eng: The OpenRISC 1200 (OR1200) is a synthesizable CPU core maintained by developers at OpenCores.org. The OR1200 design is an open source implementation of the OpenRISC 1000 RISC architecture . Architecture The IP core of the OR1200 is implemented in the Verilog HDL. As an open source core, the design is fully public and may be downloaded and modified by any individual. The official implementation is maintained by developers at OpenCores.org. The implementation specifies a power management unit, debug unit, tick timer, programmable interrupt controller, central processing unit (CPU), and memory management hardware. Peripheral systems and a memory subsystem may be added using the processor's implementation of a standardized 32-bit Wishbone bus interface. The OR1200 is intended to have a performance comparable to an ARM10 processor architecture. |
