e/TRIPS architecture

Information
has gloss	eng: TRIPS is a new microprocessor architecture being designed by a team at the University of Texas at Austin in conjunction with IBM, Intel, and Sun Microsystems. TRIPS uses a new instruction set architecture that is designed to be easily broken down into large groups of instructions (graphs) that can be run on independent processing elements. The design collects related data into the graphs, attempting to avoid expensive data reads and writes and keeping the data in high speed memory close to the processing elements. The prototype TRIPS processor contains 16 such elements, but it is expected this will rapidly scale up to 128 in "real world" processors in the near future. Combined with a number of architecture changes, the TRIPS design hopes to reach 1 TFLOP on a single processor by 2012.
lexicalization	eng: TRIPS architecture
instance of	(noun) integrated circuit semiconductor chip that performs the bulk of the processing and controls the parts of a system; "a microprocessor functions as the central processing unit of a microcomputer"; "a disk drive contains a microprocessor to handle the internal functions of the drive" microprocessor

Meaning
German
has gloss	deu: Der TRIPS-Prozessor (Tera-op, Reliable, Intelligently adaptive Processing System) ist ein Forschungsprozessor der University of Texas at Austin. Die Prozessorarchitektur ist so ausgelegt, dass sich weitere Kerne möglichst einfach hinzufügen lassen. Das Projekt wird von IBM und der DARPA gefördert.
lexicalization	deu: TRIPS-Prozessor
Italian
has gloss	ita: TRIPS (The Tera-op, Reliable, Intelligently adaptive Processing System) è unarchitettura per microprocessori sviluppata da un gruppo di ricerca dellUniversity of Texas at Austin con lIBM. TRIPS utilizza un nuovo instruction set sviluppato per poter essere suddiviso in blocchi di istruzioni indipendenti in modo da poter essere eseguita da unità di esecuzione indipendenti. Il prototipo del processore basato sullarchitettura TRIPS contiene 16 elementi, ma il gruppo di ricerca ritiene di poter facilmente accrescere il parallelismo fino a 128 elementi in un processore utilizzabile per applicazioni reali. Sfruttando le innovazioni portate dalla nuova architettura il team di sviluppo ritiene di poter sviluppare processori in grado di eseguire 1 TeraFlops su singolo integrato entro il 2012.
lexicalization	ita: architettura TRIPS

Media
media:img	TRIPS Data Tile.svg
media:img	TRIPS Execution Tile.svg
media:img	TRIPS Global Control Tile.svg
media:img	TRIPS Instruction Tile.svg
media:img	TRIPS Register Tile.svg
media:img	TRIPS-Architektur.svg
media:img	TRIPS-Prototype Layout.jpg
media:img	TRIPS-Prototype Layout2.jpg
media:img	TRIPS-Prototype Package.jpg
media:img	TRIPS-Prototype Tiles Layout.svg
media:img	TRIPS-Tiles.svg
media:img	Trips diephoto rot.jpg
media:img	Trips floorplan.jpg